1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method for driving a plasma display panel, which can prevent erratic discharge of the plasma display panel caused by high temperature.
2. Background of the Related Art
The plasma display panel (hereafter called as “PDP”) is a device for displaying a picture including characters, or graphics by making phosphor luminescent by a UV ray emitted when inert gas mixture (He+Xe, Ne+Xe, or He+Xe+Ne) discharges. The PDP has advantages in that fabrication of a large sized thin PDP is easy, and provides a picture quality improved significantly owing to recent technical development.
Typically, the PDP is provided with three electrodes driven by an AC voltage, which is called as an AC surface discharge type PDP. The AC surface discharge type PDP has advantages of a low voltage drive and a long lifetime because wall charges are accumulated on a surface during discharge, and electrodes are protected from sputtering caused by the discharge.
A discharge cell of an AC PDP of surface discharge type having 3-electrodes is provided with a scan electrode Y and a sustain electrode Z formed on a front substrate, and an address electrode X formed on a back substrate. The address electrode X is formed in a direction perpendicular to a direction of the address electrode X and the scan electrode Y.
There are a front dielectric and a protective layer stacked on the front substrate having the scan electrode Y and the sustain electrode Z formed in parallel. The wall charges generated in the plasma discharge are accumulated on the front dielectric.
The protective layer prevents the front dielectric from damage caused by sputtering during the plasma discharge, and enhances an emissive efficiency of secondary electrons. In general, the protective film is formed of magnesium oxide MgO.
There are back dielectric and barrier ribs on the back substrate having the address electrode X formed thereon. Phosphor is coated on surfaces of the back dielectric and the barrier ribs.
The barrier ribs are formed in parallel with the address electrode X, for prevention of optical, electrical interference between adjacent cells on the back substrate. That is, the barrier ribs prevent leakage of the UV ray and visible light produced by discharge to adjacent discharge cells.
The phosphor is excited by the UV ray emitted during the plasma discharge, to emit one of red, green, or blue visible light. A discharge space formed between the two substrates has inert gas mixture (He+Xe, Ne+Xe, or He+Xe+Ne) injected therein for gas discharge.
Referring to FIG. 1, the discharge cells have an array of a matrix. As shown in the electrode arrangement in FIG. 1, one discharge cell 1 is provided with scan electrodes Y1-Ym and sustain electrodes Z1-Zm running in parallel, and there is a discharge cell at every crossing part of the parallel two electrodes Y1-Ym and Z1-Zm, and the address electrodes X1-Xm.
The AC PDP of surface discharge type having 3-electrodes has a driving time period required for displaying one frame of a particular gradation divided into a plurality of sub-fields. The gradation can be displayed by making emission of light for a number of times proportional to a weight of a video data in each of sub-field duration.
One example of a frame structure for driving a related art PDP is illustrated in FIG. 2. That is, FIG. 2 illustrates a display time period of one frame expressed in 256 gradations in a related art PDP.
Referring to FIG. 2, the AC PDP of surface discharge type having 3-electrodes is driven, with one frame time divided into a plurality of sub-fields each having a number of light emission times different from each other, for expressing gradations of a picture.
For an example, referring to FIG. 2, if a picture is displayed in 256 gradations by using an 8 bit of video data, one frame display time period (for an example, 1/60 seconds=approx. 16.7 msec) at each of the discharge cells is time divided into 8 sub-fields SF1-SF8.
Each of the sub-fields SF1-SF8 is divided into a reset period for initializing an entire screen, an address period for selecting cells, and a sustain period for sustaining discharges at the selected cells. Particularly, each of the reset period and the address period is given a time weight in an equal ratio in every sub-field. However, the sustain period of each of the sub-fields is given a time weight different from each other in a ratio of 2n(n=0, 1, 2, 3, - - - , 7). That is, time weights in a ratio of 1:2:4:8:16:32:64:128 are given from the first sub-field SF1 to the eighth sub-field SF8.
FIG. 3 illustrates waveform diagrams showing an example of driving waveforms of a PDP according to a frame shown in FIG. 2.
Referring to FIG. 3, each of the sub-fields of a related art PDP is divided into a reset period for resetting an entire screen, an address period for selecting cells, and a sustain period for sustaining discharge of the selected cells.
The reset period is divided into a set up time period and a set down time period. In the set up time period, a reset pulse of ramp-up waveform is provided to the scan electrode, and, in the set up time period, a reset pulse of ramp-down waveform is provided to the scan electrode.
In the reset period, a reset pulse of ramp-up waveform (RP) is provided to the scan electrode Y in the set-up period SU. The reset pulse of ramp-up waveform (RP) causes a set up discharge at the discharge cells on the entire screen. The set up discharge causes to accumulate wall charges of positive polarity (+) on the address electrodes X and the sustain electrodes Z, and wall charges of negative polarity (−) on the sustain electrodes Y.
Then, in the set-down period SD, a reset pulse of ramp-down waveform (−RP) is provided to each of the scan electrodes Y. The reset pulse of ramp-down waveform (−RP) has a declining waveform starting from a voltage of positive polarity lower than a peak voltage of a reset pulse of ramp-up waveform (RP) after the reset pulses of ramp-up waveform (RP) is provided.
The reset pulse of ramp-down waveform (−RP) causes a weak erasure discharge (=set-down discharge) at each of the discharge cells to erase a portion of the wall charges from respective electrodes X, Y, and Z formed excessively, so that the wall charges remain at each of the discharge cells uniformly enough to cause stable address discharge by the set-down discharge.
In this instance, the reset pulse of ramp-down waveform (−RP) drops down, not to a scan reference voltage (−Vw) of negative polarity (−), but to a reset down voltage Vrd higher than the scan reference voltage (−Vw) of negative polarity (−) by ΔV.
In the reset pulse of ramp-down waveform (−RP) is provided to each of the scan electrodes Y, a first DC voltage Zdc1 of positive polarity (+) is provided to each of the su stain electrodes Z That is, at the time the reset pulse of ramp-down waveform (−RP) is provided, the first DC voltage Zdc1 of positive polarity (+) is started to be provided to the sustain electrodes Z. The first DC voltage Zdc1 is maintained until the reset pulse of ramp-down waveform (−RP) reaches to the reset down voltage Vrd of negative polarity (−).
In the address period, in succession to the first DC voltage Zdc1, a second DC voltage Zdc2 of positive polarity (+) is provided to the sustain electrodes Z. The second DC voltage Zdc2 has a level lower than the first DC voltage Zdc1, because the second DC voltage Zdc1 is not required to be high owing to the reset down voltage Vrd provided in the reset period.
When the second DC voltage Zdc1 is provided to the sustain electrodes Z, a scan pulse SP of negative polarity (−) is provided to the scan electrodes Y, and a data pulse DP of positive polarity (+) synchronized to the scan pulse SP of negative polarity (−) is provided to the address electrodes X. In this instance, the scan pulse SP of negative polarity (−) has a level of the scan reference voltage −Vw lower than the reset-down voltage provided in the set-down SD period.
As a voltage difference of the scan pulse SP and the data pulse DP is added to a voltage caused by the wall charges produced in the reset period, there is an address discharge caused at the discharge cell the data pulse DP is provided thereto.
The wall charges are formed at the discharge cells selected by the address discharge enough to cause discharge when the sustain voltage is provided thereto. For causing the sustain discharge at the discharge cells selected by the address discharge, the sustain pulse SUSPy and SUSPz is provided to the scan electrodes Y and the sustain electrodes Z alternately in the sustain period.
Each of the discharge cells selected by the address discharge has a sustain discharge, i.e., a display discharge, occurred between the scan electrode Y and the sustain electrode Z every time the sustain pulse SUSPy, or SUSPz is provided thereto as a voltage owing to the sustain pulse SUSPy, or SUSPz is added to a wall voltage (a voltage caused by the wall charges).
The sustain pulse SUSPy, or SUSPz has a pulse width in a range of 2-3 μs for stabilization of the sustain discharge. This is because, though discharges substantially within a range of 0.5-1 μs are occurred after the time the sustain pulse SUSPy or SUSPz applied, it is required that the sustain pulse SUSPy, or SUSPz maintains the sustain voltage Vs for a period substantially in a range of 2-3 μs after the discharges for forming the wall charges enough to cause the next discharge.
After the sustain discharge is finished, an erasure pulse of ramp waveform having small pulse width and voltage level (not shown) is provided to the sustain electrode Z, thereby erasing the wall charges remained in the cells on an entire screen.
If the erasure pulse is provided to the sustain electrode Z, a voltage difference between the sustain electrode Z and the scan electrode Y becomes greater gradually, until weak discharges are occurred between the sustain electrode Z and the scan electrode Y, continuously. The weak discharges occurred thus erase the wall charges at the cells having the sustain discharge occurred.
However, referring to FIG. 4, if the related art PDP is operated at a high temperature, the low second DC voltage Zdc2 and data pulse voltage form excessive wall charges between the scan electrode Y and the sustain electrode Z, which causes erratic discharge between the scan electrode Y and the sustain electrode Z in the address period, making display of a right gradation impossible.